This invention relates to semiconductor devices, and more specifically relates to a novel structure for increasing the ability of the device to withstand reverse voltage.
It is well known that a semiconductor device can break down through the bulk of its body without being damaged but that breakdown across the edge of the device will cause excessive localized heating which will damage the device. Consequently, the use of guard rings is known which, in effect, reduce the thickness of the semiconductor at its center to encourage the device to break down within its bulk at a lower voltage than would cause breakdown at its edge. Wafer edge geometries, particularly tapers of various shapes, have been used to improve the field distribution across the wafer edge and to increase the reverse voltage which can be withstood across the wafer edge. Examples of prior U.S. patents using guard rings and particular edge geometries are Nos. 3,922,709, 3,984,859, 4,040,084, and 4,047,196.
The problem of providing a suitable edge taper is aggravated for the case of P-I-N type devices where the taper direction desired for the P-N junction is wrong for the N, N+ junction (or, P, P+ junction). Thus wedge-shaped configurations have been suggested for the edge of the device. However, the manufacture of a wedge-shaped cut-out in the edge of a very thin wafer is difficult and the structure is not commercially feasible.
The use of a P-I-N structure is very desirable for high voltage devices since the P-I-N structure permits the use of a thinner wafer than a conventional P-N structure and reduces the forward voltage drop of the device and increases its recovery speed. However, when a thinner wafer is used, the field gradient across the edge of the wafer is increased and the devices require very sharp tapers, frequently less than six degrees. This sharp taper is very hard to make since the sharp wafer edge tends to chip or crack and the device becomes very fragile. Moreover, the current carrying area of the device is greatly reduced.